The present invention relates generally to dynamically reconfigurable hardware and computing systems, and, more particularly, to a method for system level protection of field programmable logic devices.
The development and execution of processing algorithms may be classified under two broad categories of implementation: software and hardware. An algorithm implemented in software utilizes a set of general purpose instructions that provide a high degree of flexibility in implementing a wide variety of processing tasks. However, a processor used in such software implementations has a fixed architecture, and the overhead associated with supporting its large number of general purpose instructions decreases overall performance. An algorithm implemented in hardware, on the other hand, such as an application specific integrated circuit (ASIC), is optimized for a single or limited number of processing task(s) and is dedicated to those tasks. While such hardware implementations can provide a higher performance solution, they also have the disadvantages of lower flexibility and longer time to market.
Traditional software implementations provide many advantages to the developer, including reusable processing platforms that can perform many tasks and an iterative design approach. However, these advantages come at the expense of performance. Such traditional software implementations work on an instruction basis, which limits throughput. Moreover, they suffer due to their very limited form of parallelism, a lack of dynamic reconfigurability. Microprocessor architectures used with such software implementations are not well suited for efficiently dealing with many applications that require concurrent processing, such as multimedia data and processing network protocols.
Traditional hardware implementations are optimized to provide efficient processing of a single (or a limited number of) algorithm(s). This provides a high level of performance, but since the hardware is fixed, there is limited reuse of the processing platform and the development platform does not allow for iterative development because changes to the hardware are costly and time consuming.
Since the early 1980's, field programmable gate arrays (FPGAs) have been used to provide a partial solution to the limitations encountered in traditional software and hardware implementations. FPGAs are computing devices that can implement virtually any digital circuit in hardware. In addition, many of them can be reconfigured simply by loading them with a different “hardware” program. This allows them to implement many processing algorithms with performance that approaches that of dedicated hardware while retaining the flexibility to dynamically reconfigure the implementation when necessary. This hybrid technology of reprogrammable hardware can provide many of the advantages of both hardware and software.
However, since Programmable Logic Structures (PLS), such as FPGAs, have become more pervasive as reprogrammable logic sources on larger, system-on-chip (SOC) structures, the programming of a PLS may become susceptible to subversion by programming for uses not intended by the designer of the system. In particular, a PLS may be vulnerable to a software virus type of attack. Because a PLS may define a function that, in turn, controls an outside function (e.g., motor control of a manufacturing robot), the security of the PLS can become a serious concern in designing a PLS in an SOC.
The art of using a library to store multiple functions that can then be transported across a system bus and subsequently programmed into a PLS is known in the art, as disclosed for example in U.S. Pat. No. 6,230,307 to Davis, et al. Accordingly, given such a system architecture, it becomes desirable to be able to allow only correct programming information to be written into the PLS.